Network processors NPs promise a flexible, programmable packet processing infrastructure for network systems.
As communication protocols evolve rapidly, there is increasing interest in adapting features of the processing over time and, since software is the preferred way of expressing complex computation, we are interested in finding a platform to execute packet processing software with the best possible throughput.
Because FPGAs are widely used in network equipment and they can implement processors, we are motivated to investigate executing software directly on the FPGAs. Off-the-shelf soft processors on FPGA fabric are currently geared towards performing embedded sequential tasks and, in contrast, network processing is most often inherently parallel between packet flows, if not between each individual packet.
Our goal is to allow multiple threads of execution in an FPGA to reach a higher aggregate throughput than commercially available shared-memory soft multi-processors via improvements to the underlying soft processor architecture.
We study a number of processor pipeline organizations to identify which ones can scale to a larger number of execution threads and find that tuning multithreaded pipelines can provide compact cores with high throughput.
We then perform a design space exploration of multicore soft systems, compare single-threaded and multithreaded designs to identify scalability limits an Year: Sorry, we are unable to provide the full text but you may find it at the following location s:The Third International Workshop on Overlay Architectures for FPGAs (OLAF) is held in Monterey, California, USA, on Feburary 22, and co-located with FPGA The 25th ACM/SIGDA International Symposium on Field Programmable Gate Arrays.
Overlay Architectures for FPGA-Based Software Packet Processing Martin Labrecque Doctor of Philosophy Graduate Department of Electrical and Computer Engineering University of Toronto Packet processing is the enabling technology of networked information systems such as the Internet and is usually performed with ﬁxed-function custom-made.
Abstract Overlay Architectures for FPGA-Based Software Packet Processing Martin Labrecque Doctor of Philosophy Graduate Department of . Overlay Architectures For FPGA Resource Virtualization In this work, we designed a LUT based overlay. Even though ﬁned-grained overlays exhibit an important area ence on Hardware/Software Codesign and System Synthe-sis, CODES+ISSS , part of ESWeek ’10 Sixth Embed-.
An Area-Efﬁcient FPGA Overlay using DSP Block based Time-multiplexed Functional Units Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell and Suhaib A. Fahmyy School of Computer Engineering, Nanyang Technological University, Singapore.
is to present a software-programmable hardware overlay on FPGAs to realize the ease-of-use of software programmability and the efﬁciency of custom hardware design.